 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1 4- to 6-cell li-ion battery management analog front-end isl94208 the isl94208 battery management ic is designed for use with a microcontroller and features an analog front-end with overcurrent protection for multi-cell li-ion battery packs. the isl94208 supports battery packs consisting of 4 to 6 cells in series and one or more cells in parallel. using an internal analog multiplexer, the isl94208 allows a separate microcontroller with an a/d converter to monitor each cell voltage plus intern al and external temperature. the isl94208 provides integral overcurrent and short circuit protection circuitry, an internal 3.3v voltage regulator, internal cell balancing switches, and drive circuitry for external fet devices for control of pack charge and discharge. related literature ? ISL94208EVZ evaluation kit user guide features ? software selectable overcurrent protection levels and variable protect detection times - 4 discharge overcurrent thresholds - 4 short circuit thresholds - 4 charge overcurrent thresholds - 8 overcurrent delay times (charge) - 8 overcurrent delay times (discharge) -2 short circuit dela y times (discharge) ?automatic fet turn-off and ce ll balance disable on reaching external (battery) or internal (ic) temperature limit ? automatic cell balance turn off on ic over-temperature ? integrated charge/dischar ge fet drive circuitry ? internal cell balancing fets handle up to 200ma of balancing current for each cell ? sleep operation with negative or positive edge wake-up ? <10a sleep mode applications ?power tools ? portable equipment ? battery backup systems ? military electronics b- v ss vcell4 cb4 cb2 vcell1 vcell2 cb3 vcell3 cb1 vcell5 cb5 vcell6 dsense isl94208 isref cb6 p- c reset a/d input v cc i/o chrg scl sda wkup rgo rgc temp3v tempi therm cfet dfet ao vmon int scl sda p+ vcell0 vback vfet2 vfet1 vcc csense figure 1. typical application vback june 21, 2013 fn8306.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2012, 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl94208 2 fn8306.1 june 21, 2013 pin configuration isl94208 (32 ld qfn) top view ordering information part number (notes 1, 2, 3) part marking temp range (c) package (pb-free) pkg. dwg. # isl94208irz 94208 irz -40 to +85 32 ld 5x5 qfn l32.5x5b ISL94208EVZ evaluation board 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ specia l pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs comp liant and compatible with both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-free peak reflow temper atures that meet or exceed th e pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl94208 . for more information on msl, please see tech brief tb363 temp3v vmon cfet rgc wkup 1 24 dfet cb6 vcell5 2 3 4 5 23 22 21 20 csense dsense vback vcell1 vcell3 vfet1 7 19 14 13 12 cb2 vcell2 31 32 30 29 28 91011 cb5 vcell4 cb4 6 vcell0 15 sda 18 tempi 27 cb1 rgo ao 26 vcell6 vss 17 cb3 8 scl 25 vfet2 16 vcc isref pad pin descriptions pin number pin name description 1vcc vcc supply. this pin provides the operating voltage for the ic circuitry. connect to the positive terminal of the battery pack through a filter. 14, 12, 10, 8, 6, 4, 2 vcell0, vcell1, vcell2, vcell3, vcell4, vcell5, vcell6 battery terminal n voltage input. for n = 1 to 6, vcelln connects to the positive terminal of celln and the negative terminal of celln + 1. 13 vback sleep mode backup supply. this pin is used to power the logic when the device is asleep and the rgo output turns off. 31, 32 vfet1, vfet2 fet drivers power supply. these pins are used to provide the reference voltages for the power fet gate drivers. typically vfet2 connects to vcell3 (or equivalent vo ltage) and vfet1 connects to vcell2 (or equivalent voltage). 15,11, 9 7, 5, 3 cb1, cb2, cb3, cb4, cb5, cb6 cell balancing fet driver output n (n = 1 to 6). an internal fet between the cbn and the vcell(n - 1) can be turned on to discharge celln more than other cells, or to shunt some of the charging current away from celln. this function is used to reduce the voltage on an individual cell relative to other cells in the pack. the cell balancing fets are turned on or off by an external controller, using the i 2 c interface. 16 vss ground . this pin connects to the most negative terminal in the battery string. isl94208 3 fn8306.1 june 21, 2013 17 isref current sense reference. this input provides a separate reference point for the charge and discharge current monitoring circuits. with a separate reference connection, it is possible to minimize errors that result from voltage drops on the ground lead when the load is dr awing large currents. if a separate reference is not necessary, connect this pin to vss. 18 dsense discharge current sense monitor. this input monitors the discharge curr ent by monitoring a voltage across a sense resistor, or across the discharge path fet, or by using a fet with a current se nse pin. the voltage on this pin is measured with reference to isref. 19 csense charge current sense monitor. this input monitors the charge current by monitoring a voltage across a sense resistor, or the voltage across the charge path fet, or by using a fet with a curren t sense pin. the voltage on this pin is measured with reference to isref. 20 dfet discharge fet control. the isl94208 controls the gate of a discharg e path fet through this pin. the power fet is an n-channel device. the fet is turned on only by the microcontroller. the fet can be turned off by the microcontroller, but the isl94208 also turns off the fet in the event of an overcurrent or short circuit condition. if the microcontroller detects an undervoltage condition on any of the battery cells, it can turn off the discharge fet by controlling this output with a control bit. 21 cfet charge fet control. the isl94208 controls the gate of a charge path fet through this pin. the power fet is an n-channel device. the fet is turned on only by the microcontroller. the fet can be turned off by the microcontroller, but the isl94208 also turns off the fet in the event of an overcurrent condition. if the microcontroller detects an overvoltage condition on any of the battery cells, it can turn off the fet by controlling this output with a control bit. 22 vmon discharge load monitoring. in the event of an overcurrent or short circuit condition, the microcontroller can enable an internal resistor that connects between the vmon pin and vss. when the fets open because of an overcurrent or short circuit condition and the load remains, the voltage at vmon will be near the vcc voltage. when the load is released, the voltage at vmon drops be low a threshold indicating that the overcurrent or short circuit condition is resolved. at this point, the ldfail flag is cleared and operation can resume. 23 ao analog multiplexer output. the analog output pin is used to monitor the cell voltages and temperature sensor voltages. an external microcontroller selects the specific voltage being applied to the output by writing to a control register. 24 tempi temperature monitor input. the voltage across a thermistor is monitored at this pin to determine the temperature of the battery cells. when this input dr ops below temp3v/13, an external over-temperature condition is reported. the tempi voltage can be fed to th e ao output pin through an analog multiplexer to be monitored by the microcontroller. 25 temp3v temperature monitor output control. this pin outputs a voltage to be used in a divider that consists of a fixed resistor and a thermistor. the thermistor is located in cl ose proximity to the battery cells. the temp3v output is connected internally to the rgo voltage through a pmos switch only during a measurement of the temperature, otherwise the temp3v output is off. the temp3v output ca n be turned on continuously with a special control bit. microcontroller wake up control. the temp3v pin is also turned on when any of the dsc, doc, or coc bits are set. this can be used to wake up a sleeping microcontr oller to respond to overcurrent conditions with its own control mechanism. 26 rgo regulated output voltage. this pin connects to the emitter of an external npn transistor and works in conjunction with the rgc pin to provide a regulated 3.3v. the voltage at this pin provides feedback for the regulator and power for many of the isl94208 internal circui ts as well as providing the 3.3v output voltage for the microcontroller and other external circuits. 27 rgc regulated output control. this pin connects to the base of an external npn transistor and works in conjunction with the rgo pin to provide a regulated 3.3v. the rgc output provides the control signal for the external transistor to provide the 3.3v regulated voltage on the rgo pin. 28 wkup wake up voltage. this input wakes up the part when the voltag e crosses a turn-on threshold (wake up is edge triggered). the condition of the pin is reflected in the wkup bit (the wkup bit is level sensitive). wkpol bit = ?1?: the device wakes up on the rising edge of the wkup pin. the wkup bit is high only when the wkup pin voltage > threshold. wkpol bit = ?0?, the device wakes up on the falling edge of the wkup pin. the wkup bit is high only when the wkup pin voltage < threshold. pin descriptions (continued) pin number pin name description isl94208 4 fn8306.1 june 21, 2013 block diagram 29 sda serial data. this is the bidirectional data line for an i 2 c interface. this pin should be pulled up to 3.3v using a resistor. 30 scl serial clock. this is the clock input for an i 2 c communication link. this pin should be pulled up to 3.3v using a resistor. -pad thermal pad. connect to vss. pin descriptions (continued) pin number pin name description 3.3vdc regulator sda cb5 cb6 cb4 vcell6 vcell4 cb3 vcell3 cb2 vcell2 cb1 vcell0 temp3v scl rgc wkup power control dfet cfet 6 backup supply i 2 c, control logic, registers, oscillator overcurrent circuits temperature sensor circuits tempi 2 vcell1 vback vfet1 vfet2 csense dsense isref vmon rgo vcc mux level circuits balance cell shifters fet control circuitry vcell5 cell voltages ao vss isl94208 5 fn8306.1 june 21, 2013 table of contents pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 wake up timing (wkpol = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 wake up timing (wkpol = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 change in voltage source, fet control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 automatic temperature scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 discharge overcurrent/short circ uit monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 charge overcurrent monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 serial interface bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 symbol table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 battery connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 system power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 wkup pin operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 wkpol = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 wkpol = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 protection functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 overcurrent safety functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 load monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 over-temperature safety functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 analog multiplexer selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 cell balancing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 definition of cell balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 cell balance operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 external vmon/cfet protection mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 user flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 interface conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 clock and data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 acknowledge (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 operation state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 integrated charge/discharge path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 separate charge/discharge path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 isl94208 6 fn8306.1 june 21, 2013 pc board layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 qfn package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 alternate vfet power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 isl94208 7 fn8306.1 june 21, 2013 absolute maximum ratings (note 4) thermal information power supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 36.0v cell voltage, vcell vcelln (n = 5, 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to 27.0v vcelln (n = 3, 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 18.0v vcelln (n = 1, 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 9.0v vcelln - vcelln-1 (n = 1, 2, 3, 4, 5, 6) . . . . . . . . . . . . . . . . . . -0.5v to 5v vcell1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 5v vcell0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 0.5v cell balance, cb cb6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 36v cb6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v cc + 0.5v cb4, cb5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 27v cb4, cb5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v cc + 0.5v cb2, cb3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 18.0v cb1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to 7.0v cbn -vcn-1 (n = 1, 2, 3, 4, 5, 6) . . . . . . . . . . . . . . . . . . . . . . .-0.5v to 7.0v fet control vfet2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 to 18v vfet1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 to 13v vfet2-vfet1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5v cfet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18.0v to 18v cfet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-18.0v to v vfet2 + 0.5v dfet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 18v dfet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v vfet2 + 0.5v terminal voltage, scl, sda, c sense , d sense , tempi, rgo, ao, temp3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 to v rgo + 0.5v isref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .- 0.5v to v ss + 0.5 vback, rgc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 to 5v vmon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5v to 36v vmon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5v to v cc + 0.5v wkup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .- 0.5v to 27v wkup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5v to v cc + 0.5v thermal resistance (typical) ja (c/w) jc (c/w) 32 ld qfn (notes 5, 6) . . . . . . . . . . . . . . . . 30 1.7 continuous package power dissipation. . . . . . . . . . . . . . . . . . . . . . . .400mw storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions (note 4) temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c operating voltage: vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8v to 26.4v scl, sda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0v to 3.6v vback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .vcell1 or 2.0v to 4.6v vcell1 - vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0v to 4.3v vcelln - vcelln-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0v to 4.3v vfet1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 to 8.6 vfet2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 to 12.9 vfet2 - vfet1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8v to 4.5v isref - vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.1v to 0.1v (c sense - isref), (d sense - isref) . . . . . . . . . . . . . . . . . . . . -0.5v to 1.5v dfet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v fet2 cfet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v fet2 wkup (wkpol=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to v back wkup (wkpol=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 27v vmon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to v cc caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. all absolute maximum ratings and recommended operating conditions referenced to vss, unless otherwise noted. 5. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379 . 6. jc , ?case temperature? location is at the center of the ex posed metal pad on the package underside. see tech brief tb379 . electrical specifications v cc = 6v to 26.4v and -40c to +85c, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol test condition min (note 7) typ max (note 7) unit power-up condition 1 v porvcc v cc voltage (note 8) 4 6.5 v power-up condition 2 threshold (rising) v por v back - v ss (rising) (note 8) 0c to +60c 1.6 2.05 v 1.55 1.95 v power-up condition 2 threshold hysteresis v hys v back - v ss (falling) (note 8) 0.02 0.1 0.30 v 3.3v regulated voltage v rgo 0a < i rgc < 350a 3.0 3.3 3.6 v 3.3vdc voltage regulator control current limit i rgc (control current at output of rgc. recommend npn with gain of 70+) 0.35 0.50 ma isl94208 8 fn8306.1 june 21, 2013 v cc supply current i vcc1 power-up defaults, wkup pin = 0v 300 510 a i vcc2 ldmonen bit = 1, vmon floating, cfet = 1, dfet=1, wkpol bit = 1, vwkup = 10v, [ao3:ao0] bits = 03h 400 700 a i vcc3 default register settings, except sleep bit = 1. wkup pin = vcell1 1 10 a vfet1 supply current (normal or sleep mode) i vfet1 0.1 1.5 a vfet2 supply current (normal or sleep mode) i vfet3 dfet, cfet outputs floating 0.1 1 a rgo supply current i rgo1 power-up defaults, wkup pin = 0v 300 410 a i rgo2 ldmonen bit = 1, vmon floating, cfet = 1, dfet=1, wkpol bit = 1, vwkup = 10v, [ao3:ao0] bits = 03h 450 650 a i rgo3 default register settings, except sleep bit = 1. wkup pin = vcell1 0.4 1 a vback input current (falling edge wake up; wkpol = 0) (normal or sleep mode) i vback01 wkup v wkup2 (max) 7 12 a i vback02 v wkup2 (max) < wkup < 5v 0.5 3 a vback input current (rising edge wake up; wkpol = 1) (normal mode) i vback11 wkup < v wkup1 (min) or; wkup > v wkup1 (max) 0.5 3 a i vback12 v wkup1 (min) wkup v wkup1 (max) 120 300 a (sleep mode) i vback13 wkup v wkup1 (min) 180 500 a i vback14 wkup < v wkup1 (min) 0.5 3 a vcell input current (monitoring) i vcella sinking current at: vcell6 (measure vcell6 or vcell5) and vcell5 (measure vcell6 or vcell5) and vcell4 (measure vcell5) 40 65 a i vcellb sinking current at: vcell4 (measure vcell4) and vcell3 (measure vcell4 or vcell3) and vcell2 (measure vcell3) 30 50 a i vcellc sourcing current at: vcell2 (measure vcell2) and vcell1 (measure vcell2) -40 -20 a i vcelld sourcing current at: vcell1 (measure vcell1) and vcell0 (measure vcell1) -38 -18 a vcell input current differential (monitoring) i vcelldiff difference in monitoring current between vcelln and vcell(n-1); n = 1, 2, 3, 4 -2 2 a difference in monitoring current between vcelln and vcell(n-1); n = 5, 6 -4 4 a vcell input current (non-monitoring) i vcelln vcelln and vcell(n-1) (n = 1, 2, 3, 4, 5, or 6) n is a non-selected cell -1 0.1 1 a electrical specifications v cc = 6v to 26.4v and -40c to +85c, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test condition min (note 7) typ max (note 7) unit isl94208 9 fn8306.1 june 21, 2013 overcurrent/short circuit protection specifications discharge overcurrent detection threshold sense voltage relative to isref (default highlighted) v ocd v ocd = 0.10v (ocdv1, ocdv0 = 0, 0) 0.08 0.10 0.12 v v ocd = 0.12v (ocdv1, ocdv0 = 0, 1) 0.10 0.12 0.14 v v ocd = 0.14v (ocdv1, ocdv0 = 1, 0) 0.12 0.14 0.16 v v ocd = 0.16v (ocdv1, ocdv0 = 1, 1) 0.14 0.16 0.18 v charge overcurrent detection threshold sense voltage relative to isref (default highlighted) v occ v occ = 0.10v (occv1, occv0 = 0, 0) -0.12 -0.10 -0.07 v v occ = 0.12v (occv1, occv0 = 0, 1) -0.14 -0.12 -0.09 v v occ = 0.14v (occv1, occv0 = 1, 0) -0.16 -0.14 -0.11 v v occ = 0.16v (occv1, occv0 = 1, 1) -0.18 -0.16 -0.13 v short current detection threshold voltage relative to isref (default highlighted) v sc v sc = 0.20v (scdv1, scdv0 = 0, 0) 0.15 0.20 0.25 v v sc = 0.35v (scdv1, scdv0 = 0, 1) 0.30 0.35 0.40 v v sc = 0.65v (scdv1, scdv0 = 1, 0) 0.60 0.65 0.70 v v sc = 1.20v (scdv1, scdv0 = 1, 1) 1.10 1.20 1.30 v load monitor input threshold (falling edge) v vmon ldmonen bit = ?1? 1.1 1.45 1.8 v load monitor input threshold (hysteresis) v vmonh ldmonen bit = ?1? 0.25 mv load monitor current i vmon v(vmon) between vvmon and v(v cc ) 20 40 60 a short circuit time-out (default highlighted) t scd short circuit detection delay (sclong bit = ?0?) 90 190 290 s short circuit detection delay (sclong bit = ?1?) 5 10 15 ms over discharge current time-out (default highlighted) t ocd t ocd = 160ms (ocdt1, ocdt0 = 0, 0 and dtdiv = 0) 80 160 240 ms t ocd = 320ms (ocdt1, ocdt0 = 0, 1 and dtdiv = 0) 160 320 480 ms t ocd = 640ms (ocdt1, ocdt0 = 1, 0 and dtdiv = 0) 320 640 960 ms t ocd = 1280ms (ocdt1, ocdt0 = 1, 1 and dtdiv = 0) 640 1280 1920 ms t ocd = 2.5ms (ocdt1, ocdt0 = 0, 0 and dtdiv = 1) 1.25 2.50 3.75 ms t ocd = 5ms (ocdt1, ocdt0 = 0, 1 and dtdiv = 1) 2.5 5 7.5 ms t ocd = 10ms (ocdt1, ocdt0 = 1, 0 and dtdiv = 1) 5 10 15 ms t ocd = 20ms (ocdt1, ocdt0 = 1, 1 and dtdiv = 1) 10 20 30 ms electrical specifications v cc = 6v to 26.4v and -40c to +85c, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test condition min (note 7) typ max (note 7) unit isl94208 10 fn8306.1 june 21, 2013 over charge current time-out (default highlighted) t occ t occ = 80ms (occt1,occt0 = 0, 0 and ctdiv = 0) 40 80 120 ms t occ = 160ms (occt1, occt0 = 0, 1 and ctdiv = 0) 80 160 240 ms t occ = 320ms (occt1, occt0 = 1, 0 and ctdiv = 0) 160 320 480 ms t occ = 640ms (occt1, occt0 = 1, 1 and ctdiv = 0) 320 640 960 ms t occ = 2.5ms (occt1, occt0 = 0, 0 and ctdiv = 1) 1.25 2.50 3.75 ms t occ = 5ms (occt1, occt0 = 0, 1 and ctdiv = 1) 2.5 5 7.5 ms t occ = 10ms (occt1, occt0 = 1, 0 and ctdiv = 1) 5 10 15 ms t occ = 20ms (occt1, occt0 = 1, 1 and ctdiv = 1) 10 20 30 ms over-temperature protection specifications internal temperature shutdown threshold t i ntsd 125 c internal temperature hysteresis t hys temperature drop needed to restore operation after over-temperature shutdown 20 c internal over-temperature turn-on delay time t itd 128 ms external temperature output current i x t current output capability at temp3v pin 1.2 ma external temperature limit threshold t x tf voltage at v tempi ; relative to falling edge -20 0 +20 mv external temperature limit hysteresis t x th voltage at v tempi relative to 60 110 160 mv external temperature monitor delay t x td delay between activating the external sensor and the internal over-temperature detection 1ms external temperature autoscan on time t xtaon temp3v is on (3.3v) 5 ms external temperature autoscan off time t xtaoff temp3v output is off. 635 ms analog output specifications cell monitor analog output voltage accuracy v aoc [v celln - v celln-1 ]/2 - ao -15 4 30 mv cell monitor analog output external temperature accuracy v aoxt external temperature monitoring accuracy. voltage error at ao when monitoring tempi voltage (measured with tempi = 1v) -10 10 mv internal temperature monitor output voltage slope v i ntmon internal temperature monitor voltage change -3.5 mv/c internal temperature monitor output t i nt25 output at +25c 1.31 v electrical specifications v cc = 6v to 26.4v and -40c to +85c, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test condition min (note 7) typ max (note 7) unit v temp3v 13 ------------------------------ v temp3v 13 ------------------------------ isl94208 11 fn8306.1 june 21, 2013 ao output stabilization time t vsc from scl falling edge at data bit 0 of command to ao output stable within 0.5% of final value. ao voltage steps from 0v to 2v. (c ao = 10pf). (note 10) 0.1 ms cell balance specifications cell balance transistor r ds(on) r cb 5 10 ? cell balance transistor current i cb 200 ma wake up/sleep specifications device wkup pin voltage threshold (wkup pin active high - rising edge) v wkup1 wkup pin rising edge (wkpol = 1) device wakes up and sets wkup flag high 3.5 5.0 7.0 v device wkup pin hysteresis (wkup pin active high) v wkup1 hys wkup pin falling edge hysteresis (wkpol = 1) sets wkup flag low (does not automatically enter sleep mode) 100 mv input resistance on wkup r wkup resistance from wkup pin to vss (wkpol = 1) 250 360 450 k ? device wkup pin active voltage threshold (wkup pin active low-falling edge) v wkup2 wkup pin falling edge (wkpol = 0) device wakes up and sets wkup flag high v back -2.2 v back -1.8 v back -1.4 v device wkup pin hysteresis (wkup pin active low) v wkup2 hys wkup pin rising edge hysteresis (wkpol = 0) sets wkup flag low (does not automatically enter sleep mode) 200 mv device wake-up delay t wkup delay after voltage on wkup pin crosses the threshold (rising or falling) before activating the wkup bit 20 40 60 ms fet control specifications vfet1 voltage v vfet1a 5.6 10.8 v v vfet1b 0c to +85c 4.4 10.8 v vfet2 voltage v vfet2a 8.4 14.4 v v vfet2b 0c to +85c 6.6 14.4 v control outputs response time (cfet, dfet) t co bit 0 to start of control signal (dfet) bit 1 to start of control signal (cfet) 1.0 s cfet gate voltage vcfet no load on cfet v fet2 -0.5 v fet2 v dfet gate voltage vdfet no load on dfet v fet2 -0.5 v fet2 v fet turn on current (dfet) i df (on) dfet voltage = 0 to v fet2 -1.5v -20c to +85c 80 200 450 a fet turn on current (cfet) i cf (on) cfet voltage = 0 to v fet2 - 1.5v -20c to +85c 80 200 450 a fet turn off current (dfet) i df (off) dfet voltage = fet2 to 1v 100 180 ma dfet resistance to vss r df (off) vdfet < 1v (when turning off the fet) 11 ? serial interface characteristics scl clock frequency f scl 400 khz pulse width suppression time at sda and scl inputs t in any pulse narrower than the max spec is suppressed 50 ns scl falling edge to sda output data valid t aa from scl falling crossing v ih (min), until sda exits the v il (max) to v ih (min) window 0.9 s electrical specifications v cc = 6v to 26.4v and -40c to +85c, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test condition min (note 7) typ max (note 7) unit isl94208 12 fn8306.1 june 21, 2013 time the bus must be free before start of new transmission t buf sda crossing v ih (min) during a stop condition to sda crossing v ih (min) during the following start condition 1.3 s clock low time t low measured at the v il (max) crossing 1.3 s clock high time t high measured at the v ih (min) crossing 0.6 s start condition setup time t su:sta scl rising edge to sda falling edge. both crossing the v ih (min) level 0.6 s start condition hold time t hd:sta from sda falling edge crossing v il (max) to scl falling edge crossing v ih (min) 0.6 s input data setup time t su:dat from sda exiting the v il (max) to v ih (min) window to scl rising edge crossing v il (min) 100 ns input data hold time t hd:dat from scl falling edge crossing v ih (min) to sda entering the v il (max) to v ih (min) window 0 0.9 s stop condition setup time t su:sto from scl rising edge crossing v ih (min) to sda rising edge crossing v il (max) 0.6 s stop condition hold time t hd:sto from sda rising edge to scl falling edge. both crossing v ih (min) 0.6 s data output hold time t dh from scl falling edge crossing v il (max) until sda enters the v il (max) to v ih (min) window. (note 9) 0 ns sda and scl rise time t r from v il (max) to v ih (min) (notes 11, 12) 20 + 0.1 x cb 300 ns sda and scl fall time t f from v ih (min) to v il (max) (notes 11, 12) 20 + 0.1 x cb 300 ns capacitive loading of sda or scl cb total on-chip and off-chip (notes 11, 12) 10 400 pf sda and scl bus pull-up resistor off chip r out maximum is determined by t r and t f . for c b = 400pf, max is about 2k ? ~ 2.5k ? for c b = 40pf, max is about 15k ? to 20k ? (notes 11, 12) 1 k ? input leakage current (scl, sda) i li -10 10 a input buffer low voltage (scl, sda) v il voltage relative to v ss of the device. -0.3 v rgo x 0.3 v input buffer high voltage (scl, sda) v ih voltage relative to v ss of the device. v rgo x 0.7 v rgo +0.1v v output buffer low voltage (sda) v ol i ol = 1ma 0.4 v sda and scl input buffer hysteresis i 2 chyst sleep bit = 0 0.05 * v rgo v notes: 7. compliance to data sheet limits is assured by one or more methods: production test, characterization and/or design. 8. power-up of the device requires v back and vcc to be above the limits specified. 9. the device provides an internal hold time of at least 300ns for the sda signal to bridge the unidentified region of the falli ng edge of scl. 10. maximum output capacitance = 15pf. 11. these are i 2 c specific parameters and are not production tested. however, they are used to set conditions for testing to validate specifica tion. 12. limits should be considered typical and are not production tested. electrical specifications v cc = 6v to 26.4v and -40c to +85c, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test condition min (note 7) typ max (note 7) unit isl94208 13 fn8306.1 june 21, 2013 timing diagrams wake up timing (wkpol = 0) wake up timing (wkpol = 1) change in voltage source, fet control v wkup2 v wkup2h t wkup t wkup isl94208 15 fn8306.1 june 21, 2013 charge overcurrent monitor serial interface bus timing symbol table v occ t occ coc bit temp3v v csense register 1 read output 3.3v ?1? ?0? cfet output c turns on cfet 12v (assumes denocc bit is ?0?) t su:sto t high t su:sta t hd:sta t hd:dat t su:dat scl t f t low t buf t r t dh t aa sda (input timing) sda (output timing) waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance waveform inputs outputs isl94208 16 fn8306.1 june 21, 2013 registers table 1. registers addr register read/ write76543210 00h config/op status read only reserved reserved 1 wkup wkup pin status reserved reserved reserved reserved 01h operating status (note 15) read only reserved reserved xot ext over temp iot int over-temp ldfail load fail (vmon) dsc short circuit doc discharge oc coc charge oc 02h cell balance read/write reserved cb6on cb5on cb4on cb3on cb2on cb1on reserved cell balance fet control bits 03h analog out read/write uflg1 user flag 1 uflg0 user flag 0 reserved reserved ao3 ao2 ao1 ao0 analog output select bits 04h fet control read/write sleep force sleep (note 16) ldmonen turn on vmon connection reserved reserved reserved reserved cfet turn on charge fet (note 17) dfet turn on discharge fet (note 17) 05h discharge set read/write (write only if disseten bit set) denocd ocdv1 ocdv0 denscd scdv1 scdv0 ocdt1 ocdt0 turn off automatic ocd control overcurrent discharge threshold voltage turn-off automatic scd control short circuit discharge threshold voltage overcurrent discharge time-out 06h charge set read/write (write only if chseten bit set) denocc occv1 occv0 sclong long short-circuit delay ctdiv divide charge time by 32 dtdiv divide discharge time by 64 occt1 occt0 turn off automatic occ control overcurrent charge threshold voltage overcurrent charge time-out 07h feature set read/write (write only if fseten bit set) atmpoff turn off automatic external temp scan dis3 disable 3.3v reg. (device requires external 3.3v) tmp3on turn-on temp3v disxtsd disable external thermal shutdown disitsd disable internal thermal shutdown por force por diswkup disable wkup pin wkpol wake up polarity 08h write enable read/write fseten enable feature set writes chseten enable charge set writes disseten enable discharge set writes uflg3 user flag 3 uflg2 user flag 2 reserved reserved reserved 09h:ffh reserved na reserved notes: 13. a ?1? written to a control or configuration bit causes the acti on to be taken. a ?1? read from a status bit indicates that t he condition exists. 14. ?reserved? indicates that the bit or register is reserved for future expansion. when writing to addresses 2, 3, 4, and 8: wr ite a reserved bit with the value ?0?. do not write to reserved registers at addresses 09h th rough ffh. ignore reserved bits that are returned in a read op eration. 15. these status bits are automatically cleare d when the register is read. all other st atus bits are cleared when the condition is cleared. 16. this sleep bit is cleared on initial power up, by the wkup pi n going high (when wkpol = ?1?), by the wkup pin going low (when wkpol = ?0?), or by writing a ?0? to the location with an i 2 c command. 17. when the automatic responses are enabled, these bits are automa tically reset by hardware when an overcurrent or short circui t condition turns off the fets. at all other times, an i 2 c write operation controls the output to the respective fet and a read returns the current state of the fet drive output circuit (though not the actual voltage at the output pin). isl94208 17 fn8306.1 june 21, 2013 status registers table 2. config/op status register (addr: 00h) bit function description 7, 6, 3, 2, 1, 0 reserved reserved for future expansion. 5 1 this bit is always a ?1?. 4wkup wakeup pin status this bit is set and reset by hardware. when ?wkpol? is high: ? ?wkup? bit high = wkup pin > threshold voltage ? ?wkup? bit low = wkup pin < threshold voltage when ?wkpol? is low: ? ?wkup? bit high = wkup pin < threshold voltage ? ?wkup? bit low = wkup pin > threshold voltage table 3. operating status register (addr: 01h) bit function description 7, 6 reserved reserved for future expansion. 5xot ext over-temp this bit is set to ?1? when the external temperature sens or input indicates an over-temperature condition. if the over-temperature condition has cleared, this bit is reset when the register is read. 4iot int over-temp this bit is set to ?1? when the internal temperature sens or input indicates an over-temperature condition. if the over-temperature condition has cleared, this bit is reset when the register is read. 3ldfail load fail (vmon) when the vmon function is enabled (ldmonen = 1), this bit is set to ?1? by hardware when a discharge overcurrent or short circuit condition occurs. if the load fail condition is cl eared or under a light load, the bit is reset when the register is read. 2dsc short circuit this bit is set by hardware when a short circuit condition occurs during discharge. if the discharge short circuit condition is removed, the bit is reset when the register is read. 1doc discharge oc this bit is set by hardware when an overcurrent condition o ccurs during discharge. if the discharge overcurrent condition is removed, the bit is reset when the register is read. 0coc charge oc this bit is set by hardware when an overcurrent condition o ccurs during charge. if the charge overcurrent condition is removed, the bit is reset when the register is read. isl94208 18 fn8306.1 june 21, 2013 control registers table 4. cell balance control register (addr: 02h) control register bits balance bit 6 cb5on bit 5 cb4on bit 4 cb4on bit 3 cb3on bit 2 cb2on bit 1 cb1on xxxxx1cell1 on xxxxx0cell1 off xxxx1xcell2 on xxxx0xcell2 off xxx1xxcell3 on xxx0xxcell3 off xx1xxxcell4 on x x 0 x x x cell4 off x1xxxxcell5 on x0xxxxcell5 off 1xxxxxcell6 on 0xxxxxcell6 off bit 7 and bit 0 reserved table 5. analog out control register (addr: 03h) bits function description 7uflg1 user flag 1 general purpose flag usable by microcontroller software. this bit is battery backed up, even when rgo turns off. 6uflg0 user flag 0 general purpose flag usable by microcontroller software. this bit is battery backed up, even when rgo turns off. 5:4 reserved reserved for future expansion bit 3 ao3 bit 2 ao2 bit 1 ao1 bit 0 ao0 output voltage 0 0 0 0 high impedance output (low power state) remember to reset the ao3:ao0 bits to ?0000? after measurements to minimize unnecessary current draw from the cells. 0001v(v cell1 ) - v(v cell0) 0010v(v cell2 ) - v(v cell1 ) 0011v(v cell3 ) - v(v cell2 ) 0100v(v cell4 ) - v(v cell3 ) 0101v(v cell5 ) - v(v cell4 ) 0110v(v cell6 ) - v(v cell5 ) 1 0 0 0 external temperature. 1 0 0 1 internal temperature sensor voltage v(tempi). other cases reserved isl94208 19 fn8306.1 june 21, 2013 configuration registers the device is configured for sp ecific application requirements using the configuration register s. the configuration registers consist of sram memory. in the wake up state, this memory is powered by the rgo output. in a sleep state, this memory is powered by vback. table 6. fet control register (addr: 04h) bit function description 7sleep force sleep setting this bit to ?1? forces the device to go into a sleep condition. this turns off both fet outputs, the cell balance outputs and the voltage regula tor. this also resets the cfet, dfet, and cb6on:cb1on bits. the sleep bit is automatically reset to ?0? when the device wakes up. this bit does not reset the ao3:ao0 bits (if the wkup pin is active, when attempting to put the device into the sleep mode, then the sleep bit needs to be reset from ?1? to ?0? prior to setting it to ?1? to initiate sleep). 6ldmonen turn on vmon connection writing a ?1? to this bit turns on the vmon circuit. writing a ?0? to this bit turns off the vmon circuit. as such, the microcontroller has full co ntrol of the operation of this circuit. 5:2 reserved reserved for future expansion. 1 cfet setting this bit to ?1? turns on the charge fet. setting this bit to ?0? turns off the charge fet. this bit is automatically reset in the event of a charge overcurrent condition, unless the automatic response is disabled by the denocc bit. this bit is automatically reset in the event of an external over temperature condition, unless the response is disabled by the disxtsd bit. this bit is automatically reset in the event of an internal over temperature condition, unless the response is disabled by the disitsd bit. 0 dfet setting this bit to ?1? turns on the discharge fet. setting this bit to ?0? turns off the discharge fet. this bit is automatically reset in the event of a discharge overcurrent or discharge short circuit condition, unless the automatic response is disabled by the denocd or denscd bits. this bit is automatically reset in the event of an external over temperature condition, unless the response is disabled by the disxtsd bit. this bit is automatically reset in the event of an internal over temperature condition, unless the response is disabled by the disitsd bit. table 7. discharge set config register (addr: 05h) setting function description bit 7 denocd turn off automatic oc discharge control when set to ?0?, a discharge overcurrent condition automatically turns off the fets. when set to ?1?, a discharge overcurrent condit ion will not automatically turn off the fets. in either case, this conditio n sets the doc bit, which also turns on the temp3v output. bit 6 ocdv1 bit 5 ocdv0 overcurrent discharge voltage threshold 00v ocd = 0.10v 01v ocd = 0.12v 10v ocd = 0.14v 11v ocd = 0.16v bit 4 denscd turn off automatic sc discharge control when set to ?0?, a discharge short ci rcuit condition turns off the fets. when set to ?1?, a discharge short circuit condit ion does not automatically turn off the fets. in either case, the condition sets the scd bi t, which also turns on the temp3v output. bit 3 scdv1 bit 2 scdv0 short circuit discharge voltage threshold 00v scd = 0.20v 01v scd = 0.35v 10v scd = 0.65v 11v scd = 1.20v bit 1 ocdt1 bit 0 ocdt0 overcurrent discharge time-out 00t ocd = 160ms (2.5ms if dtdiv = 1) 01t ocd = 320ms (5ms if dtdiv = 1) 10t ocd = 640ms (10ms if dtdiv = 1) 11t ocd = 1280ms (20ms if dtdiv = 1) isl94208 20 fn8306.1 june 21, 2013 . table 8. charge/time scale config register (addr: 06h) setting function description bit 7 denocc turn off automatic oc charge control when set to ?0?, a charge overcurrent condition automatically turns off the fets. when set to ?1?, a charge overcurrent condition does not automatically turn off the fets. in either case, this condition sets the coc bit, which also turns on the temp3v output. bit 6 occv1 bit 5 occv0 overcurrent charge voltage threshold 00v ocd = 0.10v 01v ocd = 0.12v 10v ocd = 0.14v 11v ocd = 0.16v bit 4 sclong short circuit long delay when this bit is set to ?0?, a short circuit need s to be in effect for 190s before a shutdown begins. when this bit is set to ?1?, a short circuit needs to be in effect for 10ms before a shutdown begins. bit 3 ctdiv divide charge time by 32 when set to ?1?, the charge overcu rrent delay time is divided by 32. when set to ?0?, the charge overcurrent delay time is divided by 1. bit 2 dtdiv divide discharge time by 64 when set to ?1?, the discharge overcurrent delay time is divided by 64. when set to ?0?, the discharge overcurrent delay time is divided by 1. bit 1 occt1 bit 0 occt0 overcurrent charge time-out 00t occ = 80ms (2.5ms if ctdiv=1) 01t occ = 160ms (5ms if ctdiv=1) 10t occ = 320ms (10ms if ctdiv=1) 11t occ = 640ms (20ms if ctdiv=1) table 9. feature set configuration register (addr: 07h) bit function description 7atmpoff turn off automatic external temp scan when set to ?1? this bit disables the automatic temperature scan. when set to ?0?, the temperature is turned on for 5ms in every 640ms. 6dis3 disable 3.3v reg setting this bit to ?1? disables the internal 3.3v re gulator. setting this bit to ?1? requires that there be an external 3.3v regulator connected to the rgo pin. 5 tmp3on turn on temp 3.3v setting this bit to ?1? turns on the temp3v output to the external temperature sensor. the output will remain on as long as this bit remains ?1?. 4disxtsd disable external thermal shutdown setting this bit to ?1? disables the automatic shutdown of the cell balance and power fets in response to an external over-temperature condit ion. while the automatic response is disabled, the xot flag is set so the microcontroller can initiate a shutdown based on the xot flag. 3disitsd disable internal thermal shutdown setting this bit to ?1? disables the automatic shutdown of the cell balance and power fets in response to an internal over-temperature condition. while the automatic response is disabled, the iot flag is set so the microcontroller can initiate a shutdown based on the iot flag. 2por force por setting this bit to ?1? forces a power on reset (por ) condition. this resets all internal registers to zero. 1diswkup disable wkup pin setting this bit to ?1? disa bles the wkup pin function. caution: setting this pin to ?1? disables hardware wake up functionality. if the device then goes to sleep, it cannot be awakened without an i 2 c command that resets this bit, or by power cycling the device. 0wkpol wake up polarity setting this bit to ?1? sets the device to wake up on a rising edge at the wkup pin. setting this bit to ?0? sets the device to wake up on a falling edge at the wkup pin. when wkpol= 0, limit the maximum voltage on the wkup pin to no more than the voltage on vback. isl94208 21 fn8306.1 june 21, 2013 table 10. write enable register (addr: 08h) bit function description 7fseten enable discharge set writes when set to ?1?, allows writes to the feature set regist er. when set to ?0?, prevents writes to the feature set register (addr: 07h). default on initial power-up is ?0?. 6 chseten enable charge set writes when set to ?1?, allows writes to the charge set regist er. when set to ?0?, prevents writes to the feature set register (addr: 06h). default on initial power-up is ?0?. 5 disseten enable discharge set writes when set to ?1?, allows writes to the discharge set regi ster (addr: 05h). when set to ?0?, prevents writes to the feature set register. default on initial power-up is ?0?. 4uflg3 user flag 3 general purpose flag usable by microcontroller software . this bit is powered by the voltage on vback when rgo turns off. 3uflg2 user flag 3 general purpose flag usable by microcontroller software . this bit is powered by the voltage on vback when rgo turns off. 2, 1, 0 reserved reserved for future expansion. isl94208 22 fn8306.1 june 21, 2013 device description instructed by the microcontrolle r, the isl94208 performs cell voltage monitoring and cell ba lancing operations, overcurrent and short circuit monitoring with automatic pack shutdown using built-in selectable time delays, and automatic turn off of the power fets and cell balancing fets in an over-temperature condition. all automati c functions of the isl94208 can be turned off and the microcontroller can manage the operations through software. battery connection the isl94208 supports packs of 4 to 6 series connected li-ion cells. one connection, with input filtering components, for six cells is shown in figure 2. input capacitors are not normally needed and are not recommended. these capacitors rapidly charge when the batteries connect. this surge current is limited only by the input resistors and may be high enough to damage elements in the ic. if capacitors are needed, use the largest possible series input resistor. when using input filters, the time constants on all inputs should be the same. connection guidelines for system s using 4, 5, or 6 cells are shown in figure 3 (minus the input filters and diodes). system power-up/power-down the isl94208 powers up when the voltage on v back and v cc both exceed their por threshol d. at this time, the isl94208 wakes up and turns on the rgo output. rgo provides a regulated 3.3vdc 10% voltage at pin rgo. it does this by using a control volt age on the rgc pin to drive an external npn transistor (see figure 4). the transistor should have a beta of at least 70 to provide ample current to the device and external circuits and should have a breakdown voltage greater than 30v (preferably 50v). the voltage at the emitter of the npn transistor is monitored and regulated to 3.3v by the control signal rgc. rgo also powers most of the isl94208 internal circuits. a 500 resistor is recommended in the collector of the npn transistor to minimize initial current surge when the regulator turns on. 2.2f/35v figure 2. isl94208 input filters 500 68nf/16v 1.5k 22nf/16v 500 68nf/16v 1.5k 22nf/16v 500 68nf/35v 1.5k 22nf/35v 500 68nf/35v 1.5k 22nf/35v 500 68nf/35v 1.5k 22nf/35v 500 68nf/16v 1.5k 22nf/16v 500 68nf/16v 1k 33nf/16v 1k 33nf/16v @ 4v balance current = 2ma 20 vcell0 cb6 cb5 cb4 cb3 cb2 cb1 vcell6 vcell5 vcell4 vcell3 vcell2 vcell1 vss vcc vfet2 vback 1k 33nf/16v vfet1 27v figure 3. battery connection options note: multiple cells can be connected in parallel. vcell6 vcell5 vcell4 vcell3 vcell2 vcell1 vcell0 6 cells cb6 cb5 cb4 cb3 cb2 cb1 vcc vss vcell6 vcell5 vcell4 vcell3 vcell2 vcell1 vcell0 5 cells cb6 cb5 cb4 cb3 cb2 cb1 vcc vss vcell6 vcell5 vcell4 vcell3 vcell2 vcell1 vcell0 4 cells cb6 cb5 cb4 cb3 cb2 cb1 vcc vss vfet2 vfet1 vback vfet2 vfet1 vback vfet2 vfet1 vback isl94208 23 fn8306.1 june 21, 2013 once powered up, the device remains in a wake up state until put to sleep by the microcontroller (t ypically when the cells drop too low in voltage) or until the v back or v cc voltages drop below their por threshold. wkup pin operation there are two ways to design a wake up of the isl94208. wkpol = 0 in an active low connection (wkpol = ?0? - default), the device wakes up when the wkup pin goes low when compared to a reference based on the v back voltage. this normally happens in a pack when a charger connects to the battery terminals. to put the part to sleep, when configured as an active low wkup, if the wkup pin is high, then a single rising edge on the sleep bit puts the part to sleep. however, if the wkup pin is low, the device needs to see a falling edge of the sleep bit (or the wkup pin needs to be pulled high), before the rising edge of the sleep bit can force the device into the sleep mode. a wkup/sleep timing timing diagram for wkpo l = 0 is shown in figure 7. when using the falling edge option, the voltage on the wkup pin should not exceed the voltage on vback for extended periods of time. also, if wkup is pulled up to the vback pin (or cell1) then the connection of the charger or load should only maintain the wkup connection for a short time to minimize the drain of cell 1. also, for the falling edge option, maintaining the wkup voltage low results in higher vback current. see the electrical table. for an example wake up circuit, see figure 6. wkpol = 1 in an active high connection (w kpol = ?1?) the device wakes up when the wkup pin is pulled high, normally by a connection through an external switch. to put the part to sleep, when configured as an active high wkup, if the wkup pin is low, then a single rising edge on the sleep bit puts the part to sleep. however, if the wkup pin is high, the device needs to see a falling edge of the sleep bit, (or the wkup pin needs to be pulled low), before the rising edge of the sleep bit can force the device into the sleep mode. a wkup/ sleep timing timing diagram for wk pol = 1 is shown in figure 6. see an example wake up circuit, using the microcontroller to control wake up, in figure 6. this microcontroller would need to be powered by a separate supply. in either active low or active high wake up, there is a filter that ignores wkup pulses that are shorter than a t wkup period. if the device is in sleep mode when the wkup signal goes active, then the regulator turns on to power the wake up circuits. however, the part is not fully awake, it is in a pseudo sleep mode, until the wake up condition is latched, after which the device is fully active. when using the active high wake up option, it is not recommended that the wkup voltage remain high while the device is in sleep mode. doing so results in excessive current on the vback pin. rgc rgo vss vcc 3.3v gnd figure 4. voltage regulator circuits 500 10f isl94208 figure 5. simplified wake up control circuits vss 360k * * internal resistor only connected when wkpol = 1. 5v wkup wkpol wkup (status) (control) wake up circuits v back isl94208 24 fn8306.1 june 21, 2013 figure 6. example external wake up circuits wkup vss vback 200k 100k dfet cfet dsc- dsc+ 240k 0.47f/35v v chrg- chrg+ pack+ 15v isl94208 0.47f/35v wkpol = 0 wkup vss vback dfet cfet dsc- dsc+ v chrg- chrg+ pack+ 49.9k c isl94208 turn on to wake, then turn off 49.9k 200k 49.9k (>60ms high time) wkpol = 1 notes: 18. wkpol = 0 - the dsc- connection wakes the isl94208 when the load connects. 19. wkpol = 0 - the charger connection has three terminals. one terminal indicates that the charger is connected. 20. wkpol = 1 - this connection wakes the pack under control of a microcontroller. this microcontroller needs to be powered by a separate regulator. awake figure 7. sleep/wakeup timing (wkpol bit = 0) falling wkup pin sleep bit rgc pin wkup bit 4v 1v awake sleep edge threshold t wkup isl94208 25 fn8306.1 june 21, 2013 protection functions in the default recommende d condition, the isl94208 automatically responds to discha rge overcurrent, discharge short circuit, charge overcurrent, internal over-temperature, and external over-temperature conditions. the designer can set optional over-ride conditions that allow the response to be dictated by the microcontroller. these are discussed in the following. overcurrent safety functions the isl94208 continually monito rs the discharge current by monitoring the voltage at the cs ense and dsense pins. if that voltage exceeds a selected value for a time exceeding a selected delay, then the device enters an overcurrent or short circuit protection mode. in these modes, the isl94208 automatically turns off both power fets and hence prevents current from flowing through the terminals p+ and p-. see figure 20 on page 32. the voltage thresholds and the re sponse times of the overcurrent protection circuits are selectable for discharge overcurrent, charge overcurrent, and discharge short circuit conditions. the specific settings are determined by bits in the discharge set configuration register (addr:05h) on page 19, and the charge/ time scale configuration sc ale register (addr:06h) on page 20. in addition, refer to ?registers? on page 16. in an overcurrent condition, th e isl94208 automatically turns off the voltage on cfet and dfet pins. the dfet output drives the discharge fet gate low, turning off the fet quickly. the cfet output turns off and allows the gate of the charge fet to be pulled low through a resistor. by turning off the fets the isl94208 prevents damage to the battery pack caused by excessive current into or out of to the cells (as in the case of a faulty charger or short circuit condition). when the isl94208 detects a discharg e overcurrent condition, both power fets are turned off and the doc bit is set. when the fets are turned off, the dfet and cfet bi ts are also reset. the automatic response to overcurrent during discharge is prevented by setting the denocd bit to ?1?. the external microcontroller can turn on the fets at any time to recover from this co ndition, but it would usually turn on the load monitor function first (by setting the ldmonen bit) and monitor the ldfail bit to detect that the overcurrent condition has been removed. when the isl94208 detects a discharg e short circuit condition, both power fets are turned off and dsc bit is set. when the fets are turned off, the dfet and cfet bi ts are also reset. the automatic response to short circuit during di scharge is prevented by setting the denscd bit to ?1?. the external mi crocontroller can turn on the fets at any time to recover from this co ndition, but it would usually turn on the load monitor function first (by setting the ldmonen bit) and monitor the ldfail bit to detect that the overcurrent condition has been removed. when the isl94208 detects a charge overcurrent condition, both power fets are turned off and coc bit is set. when the fets are turned off, the dfet and cfet bi ts are also reset. the automatic awake awake awake figure 8. sleep/wakeup timing (wkpol bit = 1) rising wkup pin sleep bit rgc pin wkup bit on awake sleep edge threshold t wkup t wkup isl94208 26 fn8306.1 june 21, 2013 response to overcurrent during disc harge is prevented by setting the denocc bit to ?1?. the external micr ocontroller can turn on the fets at any time to recover from this co ndition, but it would usually wait to do this until the cell voltages are not overcharged and that the overcurrent condition has been removed (or the microcontroller could wait until the pack is removed from the charger and then re-attached). an alternative method of providing the protection function, if desired by the designer, is to turn off the automatic safety response. in this case, the isl94208 devices still mo nitor the conditions and set the status bits, but takes no action in overcurrent or short circuit conditions. safety of the pack depends, instead, on the microcontroller sending commands to the isl94208 to turn off the fets. to facilitate a microcontroller response to an overcurrent condition, especially if the microcontroller is in a low power state, a charge overcurrent flag (coc), a discharg e overcurrent flag (doc), or the short circuit flag (dsc) being set causes the isl94208 temp3v output to turn on and pull high (see figure 10). this output can be used as an external interrupt by the microcontroller to wake-up quickly to handle the overcurrent condition. load monitoring the load monitor function in the isl94208 (see figure 9) is used primarily to detect that the load has been removed following an overcurrent or short circuit condit ion during discharge. this can be used in a control algorithm to prevent the fets from turning on while the overload or short circuit condition remains. the load monitor can also be used by the microcontroller algorithms after an undervoltage condition on any cells causes the fets to turn off. use of the load monitor prevents the fets from turning on while the load is still present. this minimizes the possible ?on-off-on cycles? that can occur when a load is applied in a low capacity pack. it can also be part of a system protection mechanism to prevent the load from turning on automatically - i.e. some action must be taken before the pack is again turned on. the load monitor circuit can be turned on or off by the microcontroller. it is normally turned off to minimize current consumption. it must be activated by the external microcontroller for it to operate. the circuit works by internally connecting the vmon pin to vss through a resistor. the circuit operates as shown in figure 9. in a typical pack operation, when an overcurrent or short circuit event happens, the dfet turns off, opening the battery circuit to the load. at this time, the r l is small and the load monitor is initially off. in this condition, th e voltage at vmon rises to nearly the pack voltage. once the power fets turn off, the microcontroller activates the load monitor by setting the ldmonen bit. this turns on an internal fet that adds a pull down resistor to the load monitor circuit. while still in the overlo ad condition the combination of the load resistor, an external adjustment resistor (r 1 ), and the internal load monitor resistor form a voltage divider. r 1 is chosen so that when the load is released to a sufficient level, the ldfail condition is reset. the diode in the vmon circuit is necessary to prevent the vmon voltage from going negative with respect to vss when a charger connects between p+ and p- and the charger voltage is significantly larger than the battery stack voltage. over-temperature safety functions external temperature monitoring the external temperature is moni tored by using a voltage divider consisting of a fixed resistor and a thermistor. this divider is powered by the isl94208 temp3v output. this output is normally controlled so it is on for only short periods to minimize current consumption. without microcontroller intervention, and in the default state, the isl94208 provides an automatic temperature scan. this scan circuit repeatedly turns on temp 3v output (and the external temperature monitor) for 5ms out of every 640ms. in this way, the external temperature is monito red even if the microcontroller is asleep. when the temp3v output turns on, the isl94208 waits 1ms for the temperature reading to stabiliz e, then compares the external temperature voltage with an internal voltage divider that is set to temp3v/13. if the thermistor voltage is below the reference threshold after the delay, an external temperature fail condition exists. to set the external over-temperature limit, set the value of r x resistor to the 12 times the resi stance of the thermistor at the desired over-temp threshold. the temp3v output pin also turns on when the microcontroller sets the ao3:ao0 bits to select that the external temperature voltage. this causes the tempi voltage to be placed on ao and activates (after 1ms) the over-temperature detection. as long as the ao3:ao0 bits point to the external temperature, the temp3v output remains on. because of the manual scan of the temperature, it may be desired to turn off the automatic scan, although they can be used at the same time without interference. to turn off the automatic scan, set the atmpoff bit. figure 9. load monitor circuit vss ldmonen vmon v ref ldfail isl94208 p- = 1 if vmon >v vmonh = 0 if vmon v vmonl vss p+ r l open power fets r 1 isl94208 27 fn8306.1 june 21, 2013 the microcontroller can over-ride both the automatic temperature scan and the microcontroller controlled temperature scan by setting the temp3on configuration bit. this turns on the temp3v output to keep the temperature control voltage on all the time, for a continuous monitoring of an over-temperature condition. this likely will consume a significant amou nt of current, so this feature is usually used for special or test purposes. protection by default, when the isl94208 de tects an internal or external over-temperature condition, the fets are turned off, the cell balancing function is disabled, and the iot bit or xot bit (respectively) is set. turning off the fets in the event of an over-temperature condition prevents continued discharge or charge of the cells when they are over heated. turning off the cell balancing in the event of an over-temperature condition prevents damage to the ic in the event too many cells are being balanced, causing too much power dissipation in the isl94208. in the event of an automatic over-temperature condition, cell balancing is prevented and fets are held off until the temperature drops back below the temperature recovery threshold. during this temperature shutdown period, the microcontroller can monitor the internal temperature through the analog output pin (ao), but any writes to the cfet bit, dfet bit, or cell balancing bits are ignored the automatic response to an internal over-temperature is prevented by setting the disitsd bit to ?1?. the automatic response to an external over-temperature is prevented by setting the disxtsd bit to ?1?. in either case, it is important for the microcontroller to monitor the internal and external temperature to protect the pack and the electronics in an over-temperature condition. analog multiplexer selection the isl94208 devices can be used to externally monitor individual battery cell voltages and temperatures. each quantity can be monitored at the analog output pin (ao). the desired voltage is selected using the i 2 c interface and the ao3:ao0 bits. see figure 11 and table 5 on page 18. remember to reset the ao3:ao0 bits to ?0000? after measurements to minimize unnecessary current draw from the cells. voltage monitoring since the voltage on each of the li-ion cells are normally higher than the regulated supply voltage, and since the voltages on the upper cells is much higher than is tolerated by a microcontroller, it is necessary to both level shift and divide the voltage before it can be monitored by the microc ontroller or an external a/d converter. to get into the voltage range required by the external circuits, the voltage level shifter divides the cell voltage by 2 and references it to vss. therefore, a li-ion cell with a voltage of 4.2v becomes a voltage of 2.1v on the ao pin. temperature monitoring the voltage representing the external temperature applied at the tempi terminal is directed to the ao terminal through a mux, as selected by the ao control bits (see figures 10 and 11). the external temperature voltage is not divided by 2 as are the cell voltages. instead it is a direct reflection of the voltage at the tempi pin. a similar operation occurs when monitoring the internal temperature through the ao output, except there is no external ?calibration? of the voltage a ssociated with the internal temperature. for the internal temperature monitoring, the voltage at the output is linear with respect to temperature. see ?electrical specifications? on page 10 for information about the output voltage at +25c and th e output slope relative to temperature. cell balancing overview a typical isl94208 li-ion battery pack consists of four to six cells in series, with one or more cell s in parallel. th is combination gives both the voltage and power necessary for many battery powered applications. while the series/parallel combination of li-ion cells is common, the configur ation is not as efficient as it could be, because any capacity mismatch between series-connected cells reduces the overall pack capacity. this mismatch is greater as the number of series cells and the load current increase. cell balancing techniques increase the capacity, and the operating time , of li-ion battery packs. definition of cell balancing cell balancing is defined as the application of differential currents to individual cells (or co mbinations of cells) in a series ao rgo temp3v tempi vss i 2 c mux i 2 c temp monitor temp fail indicator figure 10. external temp erature monitoring and control registers tmp3on ao3:ao0 decode osc atmpoff charge oc discharge oc discharge sc 508ms 4ms to c xot 12r r 1ms delay external isl94208 ext temp protection circuits r x r th isl94208 28 fn8306.1 june 21, 2013 string. without cell balancing, cells in a series string receive nominally identical currents. a battery pack requires additional components and circuitry to achieve cell balancing. for the isl94208 devices, the only external components required are balancing resistors. cell balance operation cell balancing is accomplished through a microcontroller algorithm. this algorithm compares the cell voltages (a representation of the pack capacity) and turns on balancing for the cells that have the high er voltages. there are many parameters that should be co nsidered when writing this algorithm. an example cell balancing algorithm is available in the isl94208eval1z evaluation kit. the microcontroller turns on a sp ecific cell balancing switch by setting a bit in the cell balance register. each bit in the register corresponds to one cell?s balancin g control. when the bit is set, an internal cell balancing fet turns on. this connects an external resistor across the specified cell. the maximum current that can be drawn from (or bypassed around) the cell is 200ma. this current is set by selecting the value of the external resistor. figure 12 shows an example with a 200ma (maximum) balancing current. with lower balancing current, more balancing fets can be turned on at once, without exceeding the device power dissipation limits or generating excessive balanc ing current that will heat the external resistor. external vmon/cfet protection mechanisms when there is a single charge/d ischarge path, a blocking diode is recommended in the vmon to pack- path in isl94208 solution. see d1 in figure 13. this diode is to protect against a negative voltage on the vmon pin that can occur when the fets are off and the charger connects to the pack. this diode is not needed when there is a separate charge and discharge path, because the voltages on pack- (discharge) are always positive. when the pack is designed with a single set of charge/discharge fets, the isl94208 cfet pin should be protected in the event of an overcurrent or short circuit shutdown. when this happens, the fet opens suddenly. the flyback voltage from the motor windings could exceed the maximum input voltage on the cfet pin. therefore, it is recommended that an additional external series diode be placed between the cf et pin of the isl94208 and the gate of the charge fet. see diode d 3 in figure 13. this reduces the cfet gate voltage, but not significantly. finally, to protect the charge fet itself in the event of a large negative voltage on the pack- pin, zener diode d 4 is added. a large negative voltage can occur when the pack- pin goes significantly negative, while the cfet pin is being internally clamped. the zener voltage of d 4 should be less than the v gs (max) specification of the fet. ao vcell2 vss scl i 2 c figure 11. analog output monitoring diagram regs ao3:ao0 decode vcell1 vcell6 vcell7 sda 2 level shift level shift level shift level shift tempi int temp mux ext temp. mux cell isl94208 balance (reg 02h) vcell7 vss figure 12. cell balancing co ntrol example with 200ma balancing current 7654321 21 200ma 1w 21 1w vcell1 cb1 cb7 control pack- pack+ isl94208 cfet dfet d 3 d 4 d 1 1m vmon figure 13. use of a diodes for protecting the cfet and vmon pins 10m isl94208 29 fn8306.1 june 21, 2013 user flags the isl94208 contains four flags in the register area that the microcontroller can use for general purpose indicators. these bits are designated uflg3, uflg2, uflg1, and uflg0. the microcontroller can set or reset these bits by writing into the appropriate register. the user flag bits are battery backed up (by the vback pin voltage), so the contents remain even after exiting sleep mode. however, if the microcontroller sets the por bit to force a power on reset, all of the user flags ar e also reset. in addition, if the voltage on vback ever drops below the por voltage, the contents of the user flags (as well as all other register values) would be lost. i 2 c interface interface conventions the device provides an i 2 c communications interface. the protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. therefore, the isl94208 devices operate as slaves in all applications. when sending or receiving data, th e convention is that the most significant bit (msb) is sent first. therefore, the first address bit sent is bit 7. clock and data data states on the sda line can change only while scl is low. sda state changes while scl high are reserved for indicating start and stop conditions. see figure 14. start condition all commands are preceded by th e start condition, which is a high-to-low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition has been met. see figure 15. stop condition all communications must be terminated by a stop condition, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition is only issued after the transmitting de vice has released the bus. see figure 15. acknowledge (ack) acknowledge is a software convention used to indicate successful data transfer. the tran smitting device, either master or slave, releases the bus after tr ansmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge that it received the eight bits of data. see figure 16. the device responds with an acknowledge after recognition of a start condition and the correct slav e byte. if a write operation is selected, the device responds with an acknowledge after the receipt of each subsequent eigh t bits. the device acknowledges all incoming data and address bytes, except for the slave byte when the contents do not match the device?s address. in the read mode, the device transmits eight bits of data, releases the sda line, then monito r the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the devi ce continues transmitting data. the device terminates further data transmissions if an acknowledge is not detected. the master must then issue a stop condition to return the device to standby mode and place the device into a known state. . scl sda data stable data change data stable figure 14. valid data changes on i 2 c bus scl sda start stop figure 15. i 2 c start and stop bits 8 1 9 data output from transmitter data output from receiver start acknowledge figure 16. acknowledge response from receiver scl from master isl94208 30 fn8306.1 june 21, 2013 write operations for a write operation, the device requires a slave byte and a register address byte. the slave byte specifies the particular device on the i 2 c bus that the master is writing to. the register address specifies one of the registers in th at device. after receipt of each byte, the device responds with an acknowledge, and awaits the next eight bits from the master. after the acknowledge, following the transfer of data, the master terminates the transfer by generating a stop condition (see figure 17). when receiving data from the master, the value in the data byte is transferred into the register specified by the register address byte on the falling edge of the clock following the 8th data bit. after receiving the acknowledge after the data byte, the device automatically increments the address. so, before sending the stop bit, the master may send additional data to the device without re-sending the slave and register address bytes. after writing to address 0ah, the addre ss ?wraps around? to address 0. do not continue to write to addresses higher than address 08h, since these addresses access registers that are reserved. writing to these locations can result in unexpected device operation. 0 0101 00 0 s t a r t s t o p slave byte register address data a c k a c k a c k sda bus signals from the slave signals from the master figure 17. write sequence isl94208: slave byte = 50h 1 0101 00 0 s t a r t s t o p slave byte data a c k a c k figure 18. read sequence isl94208: slave byte = 010100xh 0 0101 00 0 s t a r t slave byte register address a c k a c k sda bus signals from the slave signals from the master 1 0101 00 0 s t a r t s t o p slave byte data a c k a c k random read current address read isl94208 31 fn8306.1 june 21, 2013 register protection the discharge set, charge set, and feature set configuration registers are write protected on initial power up. in order to write to these registers it is necessary to set a bit to enable each one. these write enable bits are in the write enable register (address 08h). 1. write the fseten bit (addr 8:bit 7) to ?1? to enable changes to the data in the feature set register (address 7). 2. write the chseten bit (addr 8:bit 6) to ?1? to enable changes to the data in the featur e set register (address 6). 3. write the disseten bit (addr 8:bit 5) to ?1? to enable changes to the data in the feature set register (address 5). the microcontroller can reset these bits back to zero to prevent inadvertent writes that change the operation of the pack. operation state machine figure 19 shows a device state machine, which illustrates how the isl94208 responds to various conditions. power fails and vcc or vback or both supplies do not meet minimum voltage requirements wkup goes above or below threshold (edge triggered). or, sleep bit is set to ?0? i 2 c interface is disabled. biasing is disabled. all registers set to default values (all = ?0?) power down state i 2 c interface is enabled. biasing is enabled. voltage regulator is enabled. power up state ?voltage regulator is on ? logic and registers are powered by rgo ? cfet, dfet, and cell balancing outputs are on or off. (require an external command to turn on). ? the over temperature protection circuit is active. ? overcurrent protection (ocp) circuits are active when the either of the cfet and dfet outputs are enabled. the ocp circuits are off when both the cfet and dfet outputs are off. ? overcurrent conditions force the power fets to turn off. over temperature conditions force the power fets and cell balance output off. ? voltage and temperature monitoring circuits are awaiting external control. main operating state (awake) power is applied and both vcc and vback meet minimum voltage requirements ? voltage regulator is off ? biasing is off ? logic and registers are powered by vback ? cfet, dfet, and cell balancing outputs are off. ? charge and discharge current protection circuits are off. ? voltage and temperature monitoring circuits are off. ?i 2 c communication is active (if vback voltage is high enough to operate with the external device). sleep state sleep bit (wkup not active) sleep bit figure 19. device operation state machine isl94208 32 fn8306.1 june 21, 2013 application circuits the following application circuits are ideas to consider when developing a battery pack implementation. there are many more way s that the pack can be designed. integrated charge/discharge path figure 20. 6-cell application circuit integrated charge/discharge path b- v ss vcell4 cb4 cb2 vcell1 vcell2 cb3 vcell3 cb1 vcell5 cb5 vcell6 dsense csense isl94208 isref minimize length maximize copper cb6 p-/ch- leds/ 1f resistors optional chrg scl sda wkup rgo rgc temp3v tempi therm cfet dfet ao vmon p+ 16v ( isl94208 35 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8306.1 june 21, 2013 for additional products, see www.intersil.com/en/products.html about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/ en/support/qualandreliability.html#reliability revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change june 11, 2013 fn8306.1 figure 1: updated application diagram. page 7: changed recommended operat ing conditions for wkup voltage. page 8: reduced max limit for vfet1 and vfet2 current. page 8: added several operating conditions for vback current specifications adjusted max limit to comply with the new conditions. page 8: reduced the limits for vc ell input current (non-monitoring). page 21: on the description of the wkpol bit, added the comment, ?when wkpol=0, limit the maximum voltage on the wkup pin to no more than the voltage on vback.? page 23: changed the circuit in figure 2 on the use of input filters and changed the related text. page 23: changed the circuits in figure 3 regardin g the recommended connection of fewer than 6 cells. page 24: added text describing the wkpol=0 and wkpol=1 operation and changed the example wake up circuit in figure 6. page 25: changed the comments in figure 7 to clarif y operation of external microcontroller control of wake up. page 25 and 26: added comments to figure 8 and figure 9. pages 34 and 35: updated the example applic ations circuits in figure 20 and 21. november 26, 2012 fn8306.0 initial release isl94208 36 fn8306.1 june 21, 2013 package outline drawing l32.5x5b 32 lead quad flat no-lead plastic package rev 3, 5/10 located within the zone indicate d. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 iden tifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 5.00 a 5.00 b index area pin 1 6 (4x) 0.15 32x 0.40 0.10 4 a 32x 0.23 m 0.10 c b 16 9 4x 0.50 28x 3.5 6 pin #1 index area 3 .30 0 . 15 0 . 90 0.1 base plane see detail "x" seating plane 0.10 c c 0.08 c 0 . 2 ref c 0 . 05 max. 0 . 00 min. 5 ( 3. 30 ) ( 4. 80 typ ) ( 28x 0 . 5 ) (32x 0 . 23 ) ( 32x 0 . 60) + 0.07 - 0.05 17 25 24 8 1 32 |
Price & Availability of ISL94208EVZ
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |